1.2.1. The keyboard

When the keyboard button is pressed, the console controller sets the KRF bit in CSR register. The user can poll this bit and read the keycode from the CKRR register.

If the extended keycode was sent, the bit KEXC is set in CSR register.

1.2.2. The display

User can send characters to the display by writing to register CDWR.

1.3.1 Register Mapping

Default Base Address $d000

Name	Description	Address	R/W
CSR	Console Status Register	Base + $00	R
CKRR	Console Keyboard Read Register	Base + $01	R
CDWR	Console Display Write Register	Base + $02	W

1.3.2. Console Status Register (CSR, Base + $00, Read-only)

This read-only register contains the console controller status.

Bit	Name	Description
0	KRF	Keyboard Register Full. Reading of CKRR will clear this bit.
1	KEXC	Keyboard Extended Code. The CKRR contains the extended code.
7:2	-	Reserved. Value of the bits is undetermined.

1.3.3. Console Keyboard Read Register (CKRR, Base + $01, Read-only)

This read-only register contains the keyboard key code. The incoming code will set bit KRF in CSR. KRF bit is cleared by reading CKRR.

1.3.4. Console Display Write Register (CDWR, Base + $02, Write-only)

Writing a character to this write-only register causes a character to be sent to the display.

2.2.1. The counter

The performance counter consist of one 16-bit incrementing counter. The counter is incremented at every 1ms so the counter counting frequency is 1000Hz.

NOTE. Although, the SYS8 platform only exists in the simulator, the performance counter always increments 1000 times per second. So, it can be used for real time handling.

2.3.1 Register Mapping

Default Base Address $d100

Name	Description	Address	R/W
PCLR	Performance Counter Low Register	Base + $00	R
PCHR	Performance Counter High Register	Base + $01	R

2.3.2. Performance Counter Low register (PCLR, Base + $00, Read-only)

This register contains the LSB 8-bits of the counter. Reading of PCLR causes the MSB 8-bits to be latched to the PCHR. So in effect, next read of PCHR returns the MSB value of the counter at the moment when the PCLR was read.

2.3.3. Performance Counter High register (PCHR, Base + $01, Read-only)

This register contains the MSB 8-bits of the counter. Reading of PCHR causes the LSB 8-bits to be latched to the PCLR. So in effect, next read of PCLR returns the LSB value of the counter at the moment when the PCHR was read.

3.2.1. Counter

The timer/counter consist of 16-bit decrementing counter and 16-bit latch. When enabled, the counter will decrement toward zero. After the counter reaches zero, a latch value is loaded to counter and overflow flag is set.

The counter value is decremented at every CPU cycle.

The timer can generate IRQ interrupt.

3.3.1. Register Mapping

Default Base Address of TCC0 $d200

Default Base Address of TCC1 $d210

Default Base Address of TCC2 $d220

Default Base Address of TCC3 $d230

Name	Description	Address	R/W
TCLR	Timer Counter Low Register	Base + $00	R/W
TCHR	Timer Counter High Register	Base + $01	R/W
TLLR	Timer Latch Low Register	Base + $02	R/W
TLHR	Timer Latch High Register	Base + $03	R/W
TCR	Timer Control Register	Base + $04	R/W
TIMR	Timer Interrupt Mask Register	Base + $05	R/W
TIFR	Timer Interrupt Flag Register	Base + $06	R

3.3.2. Timer Counter Low Register (TCLR, Base + $00, Read/Write)

Reading of TCLR register, returns LSB 8-bits of the actual counter. Writing to TCLR will set LSB 8-bits of the counter. Note that, to properly write all 16-bits, the timer must be stopped.

3.3.3. Timer Counter High Register (TCHR, Base + $01, Read/Write)

Reading of TCHR register, returns MSB 8-bits of the actual counter. Writing to TCHR will set MSB 8-bits of the counter. Note that, to properly write all 16-bits, the timer must be stopped.

3.3.4. Timer Latch Low Register (TLLR, Base + $02, Read/Write)

Reading of TLLR register, returns LSB 8-bits of the latch. Writing to TLLR will set LSB 8-bits of the latch. The timer should be stopped during writing to prevent overflow flag misbehaviour.

3.3.5. Timer Latch High Register (TLHR, Base + $03, Read/Write)

Reading of TLHR register, returns MSB 8-bits of the latch. Writing to TLHR will set MSB 8-bits of the latch. The timer should be stopped during writing to prevent overflow flag misbehaviour.

3.3.6. Timer Control Register (TCR, Base + $04, Read/Write)

This register controls the timer/counter.

Bit	Name	Description
0	TENA	Timer Enable. Writing one will enable timer counting.
1	OSHT	One Shot. If this bit is one when the counter reaches zero, the TENA bit is cleared, effectively stopping the timer.
2	LOAD	Load latch. Writing one will load the latch value to the Counter. Bit is always read as zero.
7:3	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

3.3.7. Timer Interrupt Mask Register (TIMR, Base + $05, Read/Write)

This register enables/disables interrupts.

Bit	Name	Description
0	OVF	Overflow interrupt enable.
7:1	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

3.3.8. Timer Interrupt Flag Register (TIFR, Base + $06, Read-only)

This register contains interrupt flags. Register is cleared by reading.

Bit	Name	Description
0	OVF	Overflow interrupt pending.
7:1	-	Reserved. Value of the bits is undetermined.

4.3.1. Register Mapping

Default Base Address of UART0 $d300

Default Base Address of UART1 $d310

Default Base Address of UART2 $d320

Default Base Address of UART3 $d330

Name	Description	Address	R/W
FFR	Frame Format Register	Base + $00	R/W
BSR	Baudrate Select Register	Base + $01	R/W
UMR	UART Mode Register	Base + $02	R/W
RHR	Receive Holding Register	Base + $03	R
THR	Transmit Holding Register	Base + $04	W
UIMR	UART Interrupt Mask Register	Base + $05	R/W
UIFR	UART Interrupt Flag Register	Base + $06	R

4.3.2. Frame Format Register (FFR, Base + $00, Read-Write)

Frame format is configured with this register.

Bit	Name	Description
0:1	DBC	Data Bit Count. 00 - 5 data bits 01 - 6 data bits 10 - 7 data bits 11 - 8 data bits
2	SBC	Stop Bit Count. 0 - 1 stop bits 1 - 2 stop bits
4:3	PS	Parity Select. 00 - no parity 01 - odd parity 10 - even parity 11 - reserved
7:5	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

4.3.3. Baudrate Select Register (BSR, Base + $01, Read-Write)

Baudrate is selected with this register.

Writing one of the following values to the register selects one baudrate to use:

• 0 - 1200
• 1 - 2400
• 2 - 4800
• 3 - 9600
• 4 - 14400
• 5 - 19200
• 6 - 38400
• 7 - 57600
• 8 - 115200

4.3.4. UART Mode Register (UMR, Base + $02, Read-Write)

UART mode register:

Bit	Name	Description
0	TXEN	Transmitter Enable.
7:1	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

4.3.5. Receive Holding Register (RHR, Base + $03, Read-Only)

Received characters are read from this register. Reading of RHR clears all the status bits in the USR register except the THRE bit. Note that, a new character is not loaded to RHR before the old character is read. So, the user must read the character as soon as possible after the arrival to prevent data loss.

4.3.6. Transmit Holding Register (THR, Base + $04, Write-Only)

If the transmitter is enabled(see UMR bit TXEN), the transmitter is activated by writing to this register. Writing to THR also clear the THRE bit in USR register.

4.3.7. UART Interrupt Mask Register (UIMR, Base + $05, Read-Write)

Bit	Name	Description
0	RHRF	Receive Holding Register Full interrupt enable.
1	THRE	Transmit Holding Register Empty interrupt enable.
2	PE	Parity Error interrupt enable.
3	FE	Framing Error interrupt enable.
4	OE	Overrun Error interrupt enable.
7:5	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

4.3.8. UART Interrupt Flag Register (UIFR, Base + $06, Read-Only)

UART status and errors can be read from this register. Bits are cleared by reading the RHR register. Except the THRE bit which is cleared by writing to THR register.

Bit	Name	Description
0	RHRF	Receive Holding Register Full interrupt pending.
1	THRE	Transmit Holding Register Empty interrupt pending.
2	PE	Parity Error interrupt pending.
3	FE	Framing Error interrupt pending.
4	OE	Overrun Error interrupt pending.
7:5	-	Reserved. Value of the bits is undetermined.

5.3.1. Register Mapping

Default Base Address $d400

Name	Description	Address	R/W
EALR	External Address Low Register	Base + $00	R/W
EAMR	External Address Middle Register	Base + $01	R/W
EAHR	External Address High Register	Base + $02	R/W
IALR	Internal Address Low Register	Base + $03	R/W
IAHR	Internal Address High Register	Base + $04	R/W
TLLR	Transfer Length Low Register	Base + $05	R/W
TLHR	Transfer Length High Register	Base + $06	R/W
MDCR	Memory DMA Command Register	Base + $07	W
MDIMR	Memory DMA Interrupt Mask Register	Base + $08	R/W
MDIFR	Memory DMA Interrupt Flag Register	Base + $09	R

5.3.2. External Address Low/Middle/High Registers (EALR/EAMR/EAHR, Base + $00-$02, Read-Write)

These three registers together form a 24-bit external address. The external address is used to access a non-volatile memory.

5.3.3. Internal Address Low/High Registers (IALR/IAHR, Base + $03-$04, Read-Write)

These two registers together form a 16-bit internal address. The internal address is used to access a system RAM memory.

5.3.4. Transfer Lenght Low/High Registers (TLLR/TLHR, Base + $05-$06, Read-Write)

These two registers together form a 16-bit transfer length.

5.3.5. Memory DMA Command Register (MDCR, Base + $07, Write-Only)

Each bit in DCR denotes a single DMA command. The user should not combine more than one command at once or the behaviour is undefined.

Bit	Name	Description
0	MWRC	Memory Write command. Transfer from RAM to non-volatile memory.
1	MRDC	Memory Read command. Transfer from non-volatile memory to RAM.
7:2	-	Reserved. Value of the bits is undetermined.

5.3.6. Memory DMA Interrupt Mask Register (MDIMR, Base + $08, Read-Write)

DMA interrupt enable bits:

Bit	Name	Description
0	MTRDY	Memory Transfer Ready interrupt enable.
1	MTERR	Memory Transfer Error interrupt enable.
7:2	-	Reserved. Value of the bits is undetermined and user should write zero to these bits.

5.3.7. Memory DMA Interrupt Flag Register (MDIFR, Base + $09, Read-Only)

These bits are cleared by reading this register.

DMA interrupt flag bits:

Bit	Name	Description
0	MTRDY	Memory Transfer Ready interrupt pending.
1	MTERR	Memory Transfer Error interrupt pending.
7:2	-	Reserved. Value of the bits is undetermined.